Memory cells of memory arrays such as volatile or non-volatile memory arrays use an interconnection structure to connect the memory cells of the array to support circuits (e.g., sense amplifiers, decoders and wordlines). Future technologies aim for smaller minimum feature sizes to increase the storage density and to reduce the cost of memory products. When scaling memory arrays down to smaller minimum feature sizes, interconnection structures also have to be scaled down. Scaling down of interconnection structures such as bitlines and bitline contacts comprising minimum feature sizes is crucial and challenging in view of feasibility of lithography, taper of contact edge or resistance of fill materials, for example.